• Inventors:
  • Assignees:
  • Publication Date: December 31, 1969
  • Publication Number:

Abstract

Claims

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (0)

    Publication numberPublication dateAssigneeTitle

NO-Patent Citations (0)

    Title

Cited By (98)

    Publication numberPublication dateAssigneeTitle
    US-2010005281-A1January 07, 2010International Business Machines CorporationPower-on initialization and test for a cascade interconnect memory system
    US-2006090106-A1April 27, 2006Evans Donald A, Ilyoung KimGeneralized BIST for multiport memories
    US-2006242483-A1October 26, 2006Rambus Inc.Built-in self-testing of multilevel signal interfaces
    US-6510530-B1January 21, 2003Nortel Networks LimitedAt-speed built-in self testing of multi-port compact sRAMs
    US-7808851-B2October 05, 2010Hynix Semiconductor Inc.Test circuit for multi-port memory device
    US-7853845-B2December 14, 2010Atmel CorporationCircuit and method for integrated circuit configuration
    US-2008304345-A1December 11, 2008Hynix Semiconductor Inc.Semiconductor memory device with reduced number of channels for test operation
    US-7203873-B1April 10, 2007Magma Design Automation, Inc.Asynchronous control of memory self test
    US-9116210-B2August 25, 2015Rambus Inc.Integrated circuit testing module including signal shaping interface
    US-6779141-B1August 17, 2004Sun Microsystems, Inc.System and method for implementing memory testing in a SRAM unit
    US-2010005375-A1January 07, 2010International Business Machines CorporationCyclical redundancy code for use in a high-speed serial link
    US-6829728-B2December 07, 2004Wu-Tung Cheng, Christopher John Hill, Omar KebichiFull-speed BIST controller for testing embedded synchronous memories
    US-2010275074-A1October 28, 2010Synopsys, Inc.Runtime programmable bist for testing a multi-port memory device
    US-7356746-B2April 08, 2008Infineon Technologies AgEmbedded testing circuit for testing a dual port memory
    US-2006125506-A1June 15, 2006Hara Dennis K, Glidden Robert MRFID tag with bist circuits
    US-7380190-B2May 27, 2008Impinj, Inc.RFID tag with bist circuits
    US-2011158013-A1June 30, 2011Hynix Semiconductor Inc.Fuse set of semiconductor memory and repair determination circuit using the same
    US-8082474-B2December 20, 2011International Business Machines CorporationBit shadowing in a memory system
    US-8139430-B2March 20, 2012International Business Machines CorporationPower-on initialization and test for a cascade interconnect memory system
    US-8286046-B2October 09, 2012Rambus Inc.Integrated circuit testing module including signal shaping interface
    US-2008016418-A1January 17, 2008Agere Systems Inc.Generalized bist for multiport memories
    US-7948786-B2May 24, 2011Micron Technology, Inc.Rank select using a global select pin
    US-7032144-B2April 18, 2006Cadence Design Systems Inc.Method and apparatus for testing multi-port memories
    US-2010005345-A1January 07, 2010International Business Machines CorporationBit shadowing in a memory system
    US-2007086253-A1April 19, 2007Gerowitz Robert G, Kenichi TsuchiyaScanned memory testing of multi-port memory arrays
    US-7979759-B2July 12, 2011International Business Machines CorporationTest and bring-up of an enhanced cascade interconnect memory system
    US-2007124629-A1May 31, 2007Infineon Technologies AgEmbedded testing circuit for testing a dual port memory
    US-8042011-B2October 18, 2011Synopsys, Inc.Runtime programmable BIST for testing a multi-port memory device
    US-2007070778-A1March 29, 2007Hynix Semiconductor Inc.Multi-port memory device with serial input/output interface
    US-2009196109-A1August 06, 2009Micron Technology, Inc.Rank select using a global select pin
    US-6317379-B1November 13, 2001Hewlett-Packard CompanyDetermine output of a read/write port
    US-2007208968-A1September 06, 2007Anand Krishnamurthy, Mumford Clint W, Lakshmikant Mamileti, Patel Sanjay BAt-speed multi-port memory array test method and apparatus
    US-2003204798-A1October 30, 2003International Business Machines CorporationOptimized ECC/redundancy fault recovery
    US-6601198-B1July 29, 2003Oki Electric Industry Co., Ltd.Semiconductor integrated circuit
    US-2004006727-A1January 08, 2004Cadence Design Systems, Inc.Method and apparatus for testing multi-port memories
    US-2010005365-A1January 07, 2010International Business Machines CorporationError correcting code protected quasi-static bit communication on a high-speed bus
    US-2009316507-A1December 24, 2009Andreev Alexandre E, Bolotov Anatoli A, Ranko ScepanovicGeneration Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories
    US-7843749-B2November 30, 2010Hynix Semiconductor Inc.Multi-port memory device with serial input/output interface
    US-6360344-B1March 19, 2002Synopsys, Inc.Built in self test algorithm that efficiently detects address related faults of a multiport memory without detailed placement and routing information
    US-6151692-ANovember 21, 2000Agilent Technologies, Inc.Integrated circuit having memory built-in self test (BIST) for different memory sizes and method of operation
    US-2005066226-A1March 24, 2005Adams R. Dean, Macdonald Eric W.Redundant memory self-test
    US-7721174-B2May 18, 2010Wu-Tung Cheng, Christopher John Hill, Omar KebichiFull-speed BIST controller for testing embedded synchronous memories
    US-7788563-B2August 31, 2010Lsi CorporationGeneration of test sequences during memory built-in self testing of multiple memories
    US-2011023741-A1February 03, 2011Hynix Semiconductor Inc.Fuse information detection circuit
    US-7949909-B2May 24, 2011Lsi CorporationAddress controlling in the MBIST chain architecture
    US-6865701-B1March 08, 2005Apple Computer, Inc.Method and apparatus for improved memory core testing
    US-7308621-B2December 11, 2007International Business Machines CorporationTesting of ECC memories
    US-8082475-B2December 20, 2011International Business Machines CorporationEnhanced microprocessor interconnect with bit shadowing
    US-7895374-B2February 22, 2011International Business Machines CorporationDynamic segment sparing and repair in a memory system
    US-2010005202-A1January 07, 2010International Business Machines CorporationDynamic segment sparing and repair in a memory system
    US-2009290436-A1November 26, 2009Hwang Hur, Chang-Ho DoTest circuit for multi-port memory device
    US-2009307543-A1December 10, 2009Alexandre Andreev, Anatoli Bolotov, Mikhail GrinchukTransport subsystem for an mbist chain architecture
    US-2009300440-A1December 03, 2009Alexandre Andreev, Anatoli Bolotov, Mikhail GrinchukData controlling in the mbist chain architecture
    US-7162672-B2January 09, 2007Rambus IncMultilevel signal interface testing with binary test apparatus by emulation of multilevel signals
    US-2010005349-A1January 07, 2010International Business Machines CorporationEnhanced microprocessor interconnect with bit shadowing
    US-2003093713-A1May 15, 2003Werner Carl W., Zerbe Jared L., Stonecypher William F., Haw-Jyh Liaw, Chang Timothy C.Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals
    US-2007074064-A1March 29, 2007Hynix Semiconductor Inc.Test circuit for multi-port memory device
    US-8046643-B2October 25, 2011Lsi CorporationTransport subsystem for an MBIST chain architecture
    US-2010005366-A1January 07, 2010International Business Machines CorporationCascade interconnect memory system with enhanced reliability
    US-6557127-B1April 29, 2003Cadence Design Systems, Inc.Method and apparatus for testing multi-port memories
    US-6550032-B1April 15, 2003Lsi Logic CorporationDetecting interport faults in multiport static memories
    US-8201069-B2June 12, 2012International Business Machines CorporationCyclical redundancy code for use in a high-speed serial link
    US-2009116323-A1May 07, 2009International Business Machines CorporationScanned memory testing of multi-port memory arrays
    US-6333872-B1December 25, 2001International Business Machines CorporationSelf-test method for testing read stability in a dual-port SRAM cell
    US-8245105-B2August 14, 2012International Business Machines CorporationCascade interconnect memory system with enhanced reliability
    US-2005066247-A1March 24, 2005Wu-Tung Cheng, Hill Christopher John, Omar KebichiFull-speed BIST controller for testing embedded synchronous memories
    WO-2010129127-A3January 20, 2011Synopsys, Inc.A runtime programmable bist for testing a multi-port memory device
    US-2011216570-A1September 08, 2011Micron Technology, Inc.Rank select using a global select pin
    US-8516338-B2August 20, 2013International Business Machines CorporationError correcting code protected quasi-static bit communication on a high-speed bus
    US-7506225-B2March 17, 2009International Business Machines CorporationScanned memory testing of multi-port memory arrays
    US-7599242-B2October 06, 2009Hynix Semiconductor Inc.Test circuit for multi-port memory device
    US-2010174955-A1July 08, 2010International Business Machines CorporationTest and bring-up of an enhanced cascade interconnect memory system
    US-7533222-B2May 12, 2009Mosys, Inc.Dual-port SRAM memory using single-port memory cell
    JP-2013097827-AMay 20, 2013Fujitsu Ltd, 富士通株式会社Integrated circuit, test circuit, test device, and test method
    US-2011251819-A1October 13, 2011Rambus Inc.Integrated circuit testing module including signal shaping interface
    US-2008016421-A1January 17, 2008International Business Machines CorporationMethod and apparatus for providing programmable control of built-in self test
    US-8111534-B2February 07, 2012Micron Technology, Inc.Rank select using a global select pin
    US-2004240308-A1December 02, 2004Sun Microsystems, Inc.Static random access memory (SRAM) unit and method for operating the same
    US-7149941-B2December 12, 2006International Business Machines CorporationOptimized ECC/redundancy fault recovery
    US-2002059543-A1May 16, 2002Wu-Tung Cheng, Hill Christopher John, Omar KebichiFull-speed bist controller for testing embedded synchronous memories
    US-8201032-B2June 12, 2012Agere Systems Inc.Generalized BIST for multiport memories
    US-8234540-B2July 31, 2012International Business Machines CorporationError correcting code protected quasi-static bit communication on a high-speed bus
    US-7882406-B2February 01, 2011Lsi CorporationBuilt in test controller with a downloadable testing program
    US-7443760-B2October 28, 2008Hynix Semiconductor Inc.Multi-port memory device with serial input/output interface
    WO-2010129127-A2November 11, 2010Synopsys, Inc.Autotest intégré (bist) programmable d'exécution pour test d'un dispositif de mémoire à ports multiples
    US-2003120974-A1June 26, 2003Cadence Design Systems, Inc.Programable multi-port memory bist with compact microcode
    US-8156391-B2April 10, 2012Lsi CorporationData controlling in the MBIST chain architecture
    US-7246279-B2July 17, 2007Sun Microsystems, Inc.Static random access memory (SRAM) unit and method for operating the same
    US-7168005-B2January 23, 2007Cadence Design Systems, Inc.Programable multi-port memory BIST with compact microcode
    US-2009282303-A1November 12, 2009Alexandre Andreev, Bolotov Anatoli ABuilt in test controller with a downloadable testing program
    US-2009058459-A1March 05, 2009Atmel CorporationAuto-trim circuit
    US-2009300441-A1December 03, 2009Alexandre Andreev, Anatoli Bolotov, Mikhail GrinchukAddress controlling in the mbist chain architecture
    JP-2015195066-ANovember 05, 2015富士通株式会社, Fujitsu LtdMemory test circuit and memory test circuit control method
    US-7865786-B2January 04, 2011International Business Machines CorporationScanned memory testing of multi-port memory arrays
    US-2010180154-A1July 15, 2010International Business Machines CorporationBuilt In Self-Test of Memory Stressor
    WO-2008002742-A3November 20, 2008Wingyu Leung, Mosys IncDual-port sram memory using single-port memory cell
    US-7755959-B2July 13, 2010Hynix Semiconductor Inc.Semiconductor memory device with reduced number of channels for test operation
    US-2010005335-A1January 07, 2010International Business Machines CorporationMicroprocessor interface with dynamic segment sparing and repair